Semiconductor Engineering

How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å

A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering.

By Semiconductor Engineering

1 min read
How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å
AI-generated illustration

Got news to share with the events industry?

Submit a press release or story tip and reach thousands of event professionals.

Get in touch→

More in Semiconductors & Microelectronics

Related Insights